Тематический план

  • Общее

    • The aim of the Research Group is to study and implement both novel computer architectures and software necessary for their application.

      RG's motto is "There is no more need to be restricted by a computer architecture - you have a problem, we create a computer to solve it".

      Research Group's members:

      • Dr., Assoc. Prof. Aleksey Popov (BMSTU, IBM) – leader of the group
      • Ph.D. Student, Ms.Sc. Vladimir Podolskiy (BMSTU, TUM), personal page
      • Ms.Sc. Stanislav Ibragimov (BMSTU, VNIIAS)

      Lower you can find short description of group's main projects.

      How to contact us:

      • write us an e-mail: alexpopov@bmstu.ru
      • give us a call: +49 1520 568 77 80 (Germany)

  • Multiple Instruction and Single Data (MISD) Computer with Separate Processing of Structures and Data

    • In the scope of this project, a unique computer architecture is developed. This architecture is a clear example of MISD class according to Flynn’s classification – the single data stream consisting both of data structures and simple variables is processed simultaneously by two cores.

      The first core, which is represented by a standard CPU, conducts arithmetical and logical operations on the contents of data structures and on simple variables. The second core, namely structures processing unit (SPU) “Leonhard”, which is another project of the Research group, conducts operations on data structures themselves: insertion and deletion of an element of data structure, intersection, union and subtraction of structures, etc. The operations supported on the level of hardware of the second core form a complete basis of operations of the mathematical sets theory. Both cores have separate memory for respective types of data processed and memory for programs that are executed by these cores. At the program execution time, the communication between cores is conducted using buffers. Currently, the MISD computer’s prototype is implemented on a FPGA board.

      Programs for MISD computer are written in a C-like programming language developed by the Research group. A program is compiled into two binary codes to be uploaded into respective cores of the MISD computer.

      Applications for MISD computer:

      • Hardware support for algorithms with a high number both of arithmetic/logical operations and operations on data structures (in general)
      • Discrete algorithms e.g. in areas:
        • Hardware supported dynamic path planning in logistics
        • Hardware supported routing in networks
        • Hardware supported motion planning algorithms in robotics
        • Certain classification algorithms

      Status:  In development, prototype available by inquiry. 

    • Papers on the project:

  • Structures processing unit (SPU) "Leonhard"

    • The structures processing unit, or processor, “Leonhard” aims to support data structures processing on the hardware level. The hardware support for such data processing operations as insertion or deletion of element to or from data structure, intersection, union, or subtraction of structures and others grants significant acceleration on the tasks requiring lots of data structures processing (e.g. operations on graphs, operations on sets of data). This is achieved by hardware representation of data structures as B+ trees in specific structures memory and by hardware support of major structures processing operations. This processor is a part of another project of the group, to name, MISD computer.

      Applications:

      • Acceleration of operations on graph databases
      • Acceleration of operations on sets

      Status:  In development, prototype available by inquiry.

  • Native compiler for MISD computer

    • The purpose of this compiler is to compile a MISD program into two separate binary files to be uploaded into respective cores of MISD computer. The compiler supports a C-like programming language including both standard arithmetical and logical operations and structures processing operations supported by SPU “Leonhard”. The main difference of the compiler from other compilers is that it supports the decomposition of the program into two separate sets of instructions for each of the MISD cores. This result is achieved by representing the initial MISD program in a form of an oriented bipartite graph with nodes depicting the corresponding operations and data entities (variables and data structures). This intermediate representation (IR) in the form of graph is further dissected into two graphs: arithmetic-logical graph (AL-graph) for CPU and structures processing graph (SP-graph) for SPU “Leonhard”. Based on acquired IRs, the compiler reconstructs abstract syntactical trees (ASTs) for each graph and further generates the binary code to be uploaded directly into program memory for respective cores.

      Moreover, the compiler provides the graphical representation of graph IRs by demand for debugging and research purposes.

      Applications:

      • Compilation of programs for MISD computer

      Status:  In development, prototype available by inquiry.

      The source code is available publically: https://github.com/Remit/misdcompiler